1. Field of the Invention
This invention relates to electronic components such as semiconductor devices, multilayer ceramic structures and multilayer thin film structures having electrical interconnection structures within the component and, more particularly, to vertical interconnect structures which electrically connect metallization on one layer of the structure to metallization on another layer and which interconnect structures and electronic components have an increased electromigration lifetime.
2. Description of Related Art
Multi-layer electronic components offer an attractive packaging solution for high performance systems such as in computer, telecommunications, military and consumer applications. These electronic components offer high density interconnections and the ability to provide increased circuitry for a given electronic component size.
In general, multilayer electronic components comprise multiple layers of a dielectric material having metallization on each layer in the form of vias, pads, straps connecting pads to vias and wiring. Vias or other openings in the dielectric layer extend from one layer to another layer and these openings are filled with a conductive material and electrically connect the metallization on one layer to the metallization on another layer and provide for the high density electronic components devices now used in industry.
An important aspect of multilayer electronic components is the via or openings between layers in which a conductive material is applied to provide electrical contact between the metallization on different layers. Broadly stated, the typical multilayer electronic component is built up from a number of layers of a dielectric material layer such as silicon oxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other dielectric materials. In the processing sequence known in the art as the "Damascene Process", the dielectric layer is patterned using known techniques such as the use of a photoresist material which is exposed to define the wiring pattern. After developing, the photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. Using the Damascene Process, openings defining wiring patterns are provided in the dielectric layer, extending from one surface of the dielectric layer to the other surface of the dielectric layer. These wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may include planarization of the metal by removing excess material with a method such as chemical mechanical polishing. In the Single Damascene Process, vias or openings are additionally provided in the dielectric layer and filled with metallization to provide electrical contact between layers of wiring levels. In the Dual Damascene Process, the via openings and the wiring pattern openings are both provided in the dielectric layer before filling with metallization. This process simplifies the procedure and eliminates some internal interfaces. These procedures are continued for each layer in the electronic component until the electronic component is completed.
In FIG. 4, a dual Damascene line of the prior art is shown. Dielectric layers and having horizontal barrier layers 16 thereon are shown comprising metallization 12 on layer 11b and metallization 12a and stud 14 in layer 11a. The stud 14 and metallization 12a are shown encased by a vertical wall of a diffusion barrier liner 15 and a horizontal liner 15a including a liner at the base of the stud which provides a diffusion barrier between the base of stud 14 and the upper surface of metallization 12. It is this type structure which has been shown to contribute to an interconnected electronic component having a low electromigration life.
The dielectric material provides electrical insulation and electrical isolation between the copper wiring elements. The openings in the dielectric layer typically called vias, when filled with a conductive material, are typically referred to as studs. The studs provide the vertical interconnections between the horizontal copper metallization on the various layers of the electronic component.
To avoid metal diffusion between the metal and the dielectric, barrier layers, also referred to as liners, are included in the structure to contain the copper or other metal and to provide improved adhesion of the copper lines and studs to the dielectric or other metallization.
For vias, the barrier layer is typically a refractory metal such as Ta or TaN and presents a barrier to the diffusion of copper metal between the via and the dielectric but also presents a barrier between the copper metal and the metallization of the underlying or overlying conductor wiring levels. Typically, the barrier layer is formed in the via on both sidewalls and at the base thereof to form the barrier layer. When the copper is plated and fills the via, the barrier layer separates the stud from the dielectric and from the lower and upper layer metallization with which the stud makes an electrical connection. It has been found that when the copper wiring in the electronic component is exposed to a high electrical circuit density for a long period of time, that the barrier layer may result in a void developing in the copper stud or metallization (depending on the direction of the current flow) and a failure by electrical open circuit may result. The time needed for this failure to occur is known as the electromigration lifetime and is a function of the stud and metallization materials and the barrier layer material.
A related application was filed on May 19, 1997 by the assignee of the present invention and is entitled "Method Of Forming A Self-Aligned Copper Diffusion Barrier In Vias" and is directed to a copper diffusion barrier formed on the sidewalls of vias.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a multilayer electronic component including components made using a single Damascene process or a dual Damascene process comprising at least one layer having through openings or vias which are filled with a conductive material to form a stud which stud electrically connects metallization on the layers and which stud and electronic component have an increased electromigration lifetime.
It is another object of the present invention to provide a method for making a multilayer electronic component having stud interconnections including components made using a single Damascene process or a dual Damascene process, wherein the stud and electronic component have an increased electromigration lifetime.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.